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1·The floating gate is positioned between the source and drain regions.

浮动栅极定位于源极区与漏极区之间。

2·The floating gate can only be accessed though another transistor, the control gate.

浮动门虽然只能进入另一个晶体管，控制闸门。

3·This work focus on the evolution ways to study the Nanocrystal floating gate non-volatile memory devices.

本文从改进型方案入手，研究了纳米晶浮栅结构的非易失性存储技术。

4·According to the structural feature of the floating gate, a nonlinear single - degree of harmonic oscillating model is set up.

根据浮体闸门的构造特征，建立了单自由度非线性振荡模型。

5·The threshold voltage of the transistor thus formed is controlled by the amount of charge that is retained on the floating gate.

如此形成的晶体管的阈值电压由保持在浮动栅极上的电荷量控制。

6·The DRAM further has a floating gate insulated from the surface and is positioned between the first region and the second region.

所述DRAM进一步包括与所述表面绝缘的浮栅，且位于所述第一区域和 所述第二区域之间。

7·The invention also discloses a fabricating method for the nanocrystal floating gate memory with the multi-media composite tunneling layer.

本发明同时公开了一种多介质复合遂穿层的纳米晶浮栅存储器的制作方 法。

8·During a read operation, the read transistor is activated to produce an output signal indicative of the charge stored in the floating gate node.

在读取操作期间，该读取晶体管被激活以产生指示储存在该浮置栅极节点中的电荷的输出信号。

9·Impact ionization arises from a charge injector (25), defining a virtual diode (30) in the substrate (20) of a floating gate charge storage transistor (11).

碰撞电离通过一在一浮栅电荷存储晶体管(11)的衬底(20)中限定一虚拟二极管(30)的电荷注入器(25)而产生。

10·Electrons are injected into the floating gate by applying a high voltage to the second impurity diffusion layer in capacitive coupling with the floating gate.

通过在与浮栅电容耦合的第二杂质扩散层上施加高电压对浮栅注入电子。