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1·An interface layer is formed on the gate dielectric layer.

在栅极电介质层上形成界面层。

2·The new research of MOSFET-gate dielectric was summarized.

本文综述了MOSFET栅介质的最新研究状况。

3·In an embodiment, the method includes forming a gate dielectric layer on a semiconductor substrate.

实施例中，本方法包括在半导体衬底上形成栅极电介质层。

4·The reliability of strain silicon, gate dielectric and copper interconnection are discussed, and some new researches are presented.

简介了应变硅材料、栅介质的工艺及铜互连的可靠性，并对新的研究方向做了介绍。

5·For a given gate dielectric, device physics require maintaining the dielectric thickness in proportion to lateral dimensions (Reference 1).

对给定的门绝缘体，设备原理上需要维持绝缘体厚度与横向尺寸成比例(参考文献1)。

6·The gate dielectric layer is deposited using a plasma enhanced deposition with a gas mixture comprising a silicon and chlorine containing compound.

门电介质沉积层使用气体包括一个芯片和含氯化合物的混合物等离子增强沉积。

7·The team is now busy working on improving the performance of the transistors by optimizing device structure, graphene quality and the gate dielectric.

现在研究者正在努力优化器件结构、石墨烯性质和栅极电介质以提高晶体管性能。

8·The at least one non-semiconductor monolayer may be positioned at depth of about 4-100 monolayers relative to the interface between the channel and the gate dielectric.

所述至少一个非半导体单层被定位于相对于所述沟道和所述栅极电介质之间的界面大约4 - 100个单层的深度处。

9·Sacrificial gate spacers are disposed on the sidewalls of the gate dielectric and gate electrode. Cavities are etched into the substrate extending under the sacrificial gate spacers.

牺牲栅电极间隔物设置在所述栅极电介质和所述栅电极的侧壁上，在所述衬底上蚀刻空腔，并且空腔在牺牲栅电极间隔物下方延伸。

10·A gate dielectric layer and a gate electrode are formed on the top surface, the opposing sidewalls of the fin and on the bottom and on the opposing sidewalls of the recess in the fin.

栅电介质层和栅极形成在鳍部的顶表面上、相对的侧壁上和鳍部内的凹陷的底部上和相对的侧壁上。