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1·The timing error detector and loop filter of HDPLL are all digitized, whereas the VCXO employs analog components.

HDPLL中定时误差检测器、环路滤波器是全数字的，而VCXO使用了模拟器件。

2·The loop is a second order phase lock loop, consisting of an interpolator, a timing error detector and a loop filter.

环路为反馈结构，包括插值器、时钟误差检测和环路滤波器三个部分。

3·EDAC error detector and corrector have been implemented to improve the reliability of register file and memory during read and write process.

针对存储器和寄存器文件增加了EDAC检错纠错器对其读写过程进行检错和纠错。

4·It is noted that the minimum mean square error (MMSE) detector often loses phase to lock a desired signal when the desired signal dips into a deep fade.

在实际通信系统中当信号处于深衰落时，最小均方误差(MMSE)检测器经常失去对信号的相位跟踪。

5·Finally, a successive interference cancellation (SIC) scheme is proposed combined with minimum mean square error (MMSE) detection. Its performance is superior to simple SIC or MMSE detector.

最后还提出了一种结合最小均方误差(MMSE)检测的连续干扰抵消(SIC)方案，其性能好于单一的SIC和MMSE检测器。

6·The relationship of the steering range of FSM and the errors corrected, the detector output and objective error, tracking control system input are analysed.

并分析了反射镜作用范围与需要校正的误差的关系，跟踪探测器输出误差信号与物方跟踪误差，以及与跟踪镜控制量的关系。

7·The experimental results of low-order modes correction for wave-front error and the enhancement of Strehl ratio in detector and the improvement of wave-front tilt are also established.

通过低阶校正模式波前误差提高了探测器接收光强，并有效校正了波前倾斜。

8·Efficiency enhanced si PIN detector and high sensitivity, large area si PIN detectors array has been developed and their sensitivity and relative error have also been simulated comprehensively.

提出了一种效率增强型硅pin探测器和新型高灵敏大面积硅pin探测器阵列的设计思想，并且对它们的探测灵敏度和相对误差进行了详细的理论模拟计算。

9·Performance analysis shows that the decision arrangement can improve the bit error rate (BER) performance of the detector.

性能分析表明，判决排序改善了检测器的误码性能。

10·It has been proved by experiment that the traditional Angle measurement algorithm of the detector with four quadrants is of big measurement error.

实验结果表明，传统的四象限探测仪测角算法具有较大的误差。