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1·Voltage threshold capability checks for logic level degradation.

阈值电压的逻辑电平降解能力的检查。

2·The input voltage at which the output logic level changes state.

输出逻辑电平改变状态时的输入电压。

3·The a data is latched if le is low and clock is held at a high or low logic level.

在一个数据锁存如果LE是低，时钟是在高或低的逻辑电平举行。

4·Most BPM engines allow you to keep a record of whatever is happening on the business logic level.

大多数BPM引擎允许您对在业务逻辑层面上发生的所有活动保持一个记录。

5·If you chose DOUT (digital out), radio buttons LOW and HIGH appear to change its logic level.

如果你选择DOUT(数字)，单选按钮高低似乎改变其逻辑电平。

6·The structural design of logic level shift and control logic circuits are dealt with in particular.

着重阐述逻辑电平转换、控制逻辑的结构设计及其工作方式。

7·The circuit supply voltage is 3 ~ 18 v, suitable in logic level of kinds of digital logical circuits.

电路的电源电压为3 ~ 18 V，适用于各种类型的数字逻辑电路的逻辑电平判断。

8·An unified method for converting MOS circuit level description into logic level description is presented.

本文介绍了一种将MOS电路级描述转换成逻辑级描述的统一方法。

9·Within the logic level the characteristics of a system are described by logical links and their timing properties.

在逻辑门级，系统的特性使用逻辑链路和它们的时间属性。

10·The most difficult problem in burst mode receiver would be signal logic level recovery and data and clock recovery.

在突发式的接收模块中，逻辑电平的恢复和时钟数据的恢复是其关键的问题。