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1·The circuits used are Chua 'circuit and phase lock loop.

所用的电路为蔡氏电路和锁相环电路。

2·How to raise the phase lock speed of embedded DPLL is researched.

对如何提高嵌入式全数字锁相环的锁定速度进行了研究。

3·Digital phase lock loop is a key part of the digital demodulator.

数字锁相环是数字解调器的关键部件。

4·The Digital Phase Lock Loop(DPLL)is the core of the coherent demodulation.

数字锁相环路（DPLL）是数字相干解调技术的核心。

5·In the new scheme proposed, the phase lock loop is avoided and the digital logical circuit is used.

该方案利用信号自身的特性，采用数字逻辑设计，有效避免了性能不高的锁相环的使用。

6·The conduction of special cable and special phase lock loop technology makes high signal more accurate;

特种的传导电缆和特殊的锁相环技术使高度信号更精准；

7·Digital phase lock loop base on fuzzy logical control, which is used to recover carrier in communication system.

基于模糊逻辑控制的数字锁相环，用于通信系统中的载波恢复。

8·The loop is a second order phase lock loop, consisting of an interpolator, a timing error detector and a loop filter.

环路为反馈结构，包括插值器、时钟误差检测和环路滤波器三个部分。

9·We have mainly researched two FM signal demodulation techniques called Frequency Spectrum Separation and Phase Lock Loop in the first part.

一次解调中研究了频谱分离法和锁相法两种实现鉴频的技术。

10·Phase lock loop and benchmark resistance compensating technologies were used to improve the detection precision, the error was less than 10%.

通过锁相放大技术及基准电阻补偿方法提高了测量的精度，误差在10%以内。